74AHC373PW集成電路（IC）的鎖存器規(guī)格書PDF中文資料

1. General description

The 74AHC373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power

Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC373 consists of eight D-type transparent latches featuring separate D-type inputs for

each latch and 3-state true outputs for bus oriented applications. A latch enable input (LE) and an

output enable input (OE) are common to all latches.

When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are

transparent, i.e. a latch output will change state each time its corresponding Dn input changes.

When pin LE is LOW, the latches store the information that is present at the Dn inputs, after a

set-up time preceding the HIGH-to-LOW transition of LE.

When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is

HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect

the state of the latches.

The 74AHC373 is functionally identical to the 74AHC573; 74AHCT573, but has a different pin

arrangement.

2. Features and benefits

? Balanced propagation delays

? All inputs have a Schmitt-trigger action

? Common 3-state output enable input

? Inputs accepts voltages higher than VCC

? Functionally identical to the 74AHC573; 74AHCT573

? Input levels at CMOS input level

? ESD protection:

? HBM EIA/JESD22-A114E exceeds 2000 V

? MM EIA/JESD22-A115-A exceeds 200 V

? CDM EIA/JESD22-C101C exceeds 1000 V

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C