74ABTH16899DGG中文資料飛利浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input.

FEATURES

? Symmetrical (A and B bus functions are identical)

? Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions

? Independent transparent latches for A-to-B and B-to-A directions

? Selectable ODD/EVEN parity

? Continuously checks parity of both A bus and B bus latches as ERRA and ERRB

? Open-collector ERR output

? Ability to simultaneously generate and check parity

? Can simultaneously read/latch A and B bus data

? Output capability: +64 mA/–32mA

? Latch-up protection exceeds 500mA per Jedec Std 17

? ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

? Power up 3-State

? Power-up reset

? Live insertion/extraction permitted

? Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs