FEATURES:

? Choose among the following memory organizations:

IDT72T7285 ? 16,384 x 72

IDT72T7295 ? 32,768 x 72

IDT72T72105 ? 65,536 x 72

IDT72T72115 ? 131,072 x 72

? Up to 225 MHz Operation of Clocks

? User selectable HSTL/LVTTL Input and/or Output

? Read Enable & Read Clock Echo outputs aid high speed operation

? User selectable Asynchronous read and/or write port timing

? 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

? 3.3V Input tolerant

? Mark & Retransmit, resets read pointer to user marked position

? Write Chip Select (WCS) input disables Write Port HSTL inputs

? Read Chip Select (RCS) synchronous to RCLK

? Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

? Program programmable flags by either serial or parallel means

? Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

? Separate SCLK input for Serial programming of flag offsets

? User selectable input and output port bus-sizing

72T7285L4-4BB屬于集成電路（IC） > FIFO 存儲器。瑞薩科技有限公司制造生產(chǎn)的72T7285L4-4BBFIFO 存儲器先入先出 (FIFO) 存儲器可用于數(shù)字信息的短期存儲，其中信息檢索順序和序列與信息存儲順序和序列相同。這類產(chǎn)品又稱為隊列或緩沖存儲器，通常用于在單獨(dú)的設(shè)備之間交換信息，尤其是在數(shù)據(jù)以不同的速率或在略微不同的時間點(diǎn)生成和使用的情況下。