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72T3685L5BBG中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

72T3685L5BBG
廠商型號

72T3685L5BBG

功能描述

2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

文件大小

564.69 Kbytes

頁面數(shù)量

58

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2024-11-16 22:58:00

72T3685L5BBG規(guī)格書詳情

FEATURES:

? Choose among the following memory organizations:

IDT72T3645 ? 1,024 x 36

IDT72T3655 ? 2,048 x 36

IDT72T3665 ? 4,096 x 36

IDT72T3675 ? 8,192 x 36

IDT72T3685 ? 16,384 x 36

IDT72T3695 ? 32,768 x 36

IDT72T36105 ? 65,536 x 36

IDT72T36115 ? 131,072 x 36

IDT72T36125 ? 262,144 x 36

? Up to 225 MHz Operation of Clocks

? User selectable HSTL/LVTTL Input and/or Output

? 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

? 3.3V Input tolerant

? Read Enable & Read Clock Echo outputs aid high speed operation

? User selectable Asynchronous read and/or write port timing

? Mark & Retransmit, resets read pointer to user marked position

? Write Chip Select (WCS) input enables/disables Write operations

? Read Chip Select (RCS) synchronous to RCLK

? Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

? Program programmable flags by either serial or parallel means

? Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

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