548AM-03LF集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Features

? Packaged in 16-pin SOIC (150 mil)

? Input clock up to 160 MHz in the non-PLL mode

? Provides clock outputs of CLK, CLK, and CLK/2

? Low skew (500 ps) on CLK, CLK, and CLK/2

? All outputs can be tri-stated

? Entire chip can be powered down by changing one or two select pins

? 3.3 V operating range

? Available in commercial and industrial temperature ranges

? RoHS 5 (green) or RoHS 6 (green and lead free) compliant package