MC14510B中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

The MC14510B synchronous up/down BCD counter is constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. The counter consists of type D flip–flop stages with a gating structure to provide type T flip–flop capability.

This counter can be preset by applying the desired value in BCD to the Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE) high. The direction of counting is controlled by applying a high (for up counting) or a low (for down counting) to the UP/DOWN input. The state of the counter changes on the positive transition of the clock input.

Cascading can be accomplished by connecting the Carry Out to the Carry In of the next stage while clocking each counter in parallel. The outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the Reset (R) pin.

This CMOS counter finds primary use in up/down and difference counting. Other applications include: (1) Frequency synthesizer applications where low power dissipation and/or high noise immunity is desired, (2) Analog–to–digital and digital–to–analog conversions, and (3) Magnitude and sign generation.

? Diode Protection on All Inputs

? Supply Voltage Range = 3.0 Vdc to 18 Vdc

? Internally Synchronous for High Speed

? Logic Edge–Clocked Design — Count Occurs on Positive Going Edge of Clock

? Asynchronous Preset Enable Operation

? Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range.