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AD6641-500EBZ開發(fā)板套件編程器的評(píng)估演示板及套件規(guī)格書PDF中文資料
廠商型號(hào) |
AD6641-500EBZ |
參數(shù)屬性 | AD6641-500EBZ 包裝為盒;類別為開發(fā)板套件編程器的評(píng)估演示板及套件;產(chǎn)品描述:BOARD EVALUATION FOR AD6641 |
功能描述 | 緩沖器/接收器 |
文件大小 |
653.3 Kbytes |
頁(yè)面數(shù)量 |
28 頁(yè) |
生產(chǎn)廠商 | Analog Devices |
企業(yè)簡(jiǎn)稱 |
AD【亞德諾】 |
中文名稱 | 亞德諾半導(dǎo)體技術(shù)有限公司官網(wǎng) |
原廠標(biāo)識(shí) | ![]() |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-3-12 19:00:00 |
人工找貨 | AD6641-500EBZ價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
AD6641-500EBZ規(guī)格書詳情
AD6641-500EBZ屬于開發(fā)板套件編程器的評(píng)估演示板及套件。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD6641-500EBZ評(píng)估和演示板及套件該系列產(chǎn)品提供了一種方便的方法,在經(jīng)過驗(yàn)證的實(shí)施環(huán)境中評(píng)估某些重點(diǎn)器件的性能或特性。評(píng)估方法通常有完善的文檔說明,并且視乎具體情況由評(píng)估軟件提供支持。產(chǎn)品通常由印刷電路板組成,板上已裝有重點(diǎn)器件以及必要或有用的支持元器件,另外也可能包括其他組件,例如電纜或電源。對(duì)于數(shù)量特別多或類別獨(dú)特的器件類別(如 ADC、DAC 和開關(guān)模式電源),評(píng)估平臺(tái)可組合為一個(gè)單獨(dú)的產(chǎn)品系列。
GENERAL DESCRIPTION
The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.
FEATURES
SNR = 65.8 dBFS at fIN up to 250 MHz at 500 MSPS
ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (?1.0 dBFS)
SFDR = 80 dBc at fIN up to 250 MHz at 500 MSPS (?1.0 dBFS)
Excellent linearity
DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical
Integrated 16k × 12 FIFO
FIFO readback options
12-bit parallel CMOS at 62.5 MHz
6-bit DDR LVDS interface
SPORT at 62.5 MHz
SPI at 25 MHz
High speed synchronization capability
1 GHz full power analog bandwidth
Integrated input buffer
On-chip reference, no external decoupling required
Low power dissipation
695 mW at 500 MSPS
Programmable input voltage range
1.18 V to 1.6 V, 1.5 V nominal
1.9 V analog and digital supply operation
1.9 V or 3.3 V SPI and SPORT operation
Clock duty cycle stabilizer
Integrated data clock output with programmable clock and
data alignment
APPLICATIONS
Wireless and wired broadband communications
Communications test equipment
Power amplifier linearization
產(chǎn)品屬性
更多- 產(chǎn)品編號(hào):
AD6641-500EBZ
- 制造商:
Analog Devices Inc.
- 類別:
開發(fā)板,套件,編程器 > 評(píng)估和演示板及套件
- 包裝:
盒
- 類型:
接口
- 功能:
緩沖器/接收器
- 使用的 IC/零件:
AD6641
- 所含物品:
板
- 描述:
BOARD EVALUATION FOR AD6641
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
Analog Devices |
24+ |
LFCSP-56 |
8623 |
全新原廠原裝,進(jìn)口正品現(xiàn)貨,正規(guī)渠道可含稅!! |
詢價(jià) | ||
Analog Devices |
24+ |
EvaluationBoard |
33680 |
ADI優(yōu)勢(shì)主營(yíng)型號(hào)-原裝正品 |
詢價(jià) | ||
ADI/亞德諾 |
21+ |
LFCSP |
1500 |
詢價(jià) | |||
ADI(亞德諾) |
23+ |
NA |
20094 |
正納10年以上分銷經(jīng)驗(yàn)原裝進(jìn)口正品做服務(wù)做口碑有支持 |
詢價(jià) | ||
ADI |
23+ |
BGAQFP |
8659 |
原裝公司現(xiàn)貨!原裝正品價(jià)格優(yōu)勢(shì). |
詢價(jià) | ||
ADI |
21+ |
NA |
21 |
全新原裝 鄙視假貨15118075546 |
詢價(jià) | ||
ADI/亞德諾 |
22+ |
LFCSP |
9000 |
原裝正品 |
詢價(jià) | ||
AD |
23+ |
NA |
8021 |
專業(yè)電子元器件供應(yīng)鏈正邁科技特價(jià)代理QQ1304306553 |
詢價(jià) | ||
ADI/亞德諾 |
21+ |
QFN56 |
7236 |
百域芯優(yōu)勢(shì) 實(shí)單必成 可開13點(diǎn)增值稅 |
詢價(jià) | ||
AD |
24+ |
QFN |
35200 |
一級(jí)代理/放心采購(gòu) |
詢價(jià) |